1. Field of the Invention
This technology relates to nonvolatile NAND memory, with neighboring memory cells arranged sequentially in a vertical dimension out of the plane of the substrate and not just in a horizontal dimension along or parallel to the plane of the substrate.
2. Description of Related Art
In Jiyoung Kim et al., “Novel 3-D Structure for Ultra High Density Flash Memory with VRAT (Vertical-Recess-Array-Transistor)” pp. 122-123, 2008 Symposium on VLSI Technology Digest of Technical Papers, incorporated by reference, stacked memory cells are arranged with the channel running in a interior region covered by the stacked gates and charge storage material. This approach separates neighboring columns of gates with intervals of horizontal channel. This approach requires the creation of multiple undercuts which must be filled with the gate electrodes.
In Jiyoung Kim et al., “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)” pp. 186-187, 2009 Symposium on VLSI Technology Digest of Technical Papers, incorporated by reference, stacked memory cells are arranged with the channel running in an exterior region covered by the stacked gates and charge storage material. In this approach, intervals of horizontally oriented channel separate neighboring stacks of gates, and intervals of vertically oriented channel run up one side and down the other side of each stack. To help reduce the off current, the stacks are each a single gate wide, with each gate controlling both of the vertically oriented lengths of channel, with one vertically oriented length of channel on each side of each gate.